Unit 1: Register Transfer, Micro-operations, and Basic Computer Organization

1. Register Transfer and Micro-operations

1.1 Register Transfer Language (RTL)

Register Transfer Language (RTL) is a symbolic notation used to describe the internal organization, register operations, and transfer of data between registers in a digital system.

Definition: RTL expresses micro-operations and hardware data flows symbolically using register names, control conditions, and directional transfer arrows.

Registers are denoted by uppercase letters (and sometimes digits) representing their functional roles, such as MAR (Memory Address Register), PC (Program Counter), IR (Instruction Register), and AC (Accumulator).

• Transfer Statement: R2 ← R1 indicates that the content of register R1 is transferred into register R2 without altering R1.
• Conditional Transfer: P: R2 ← R1 specifies that the transfer occurs if and only if control variable P = 1.

1.2 Bus and Memory Transfers

Instead of connecting every register to all other registers directly, digital systems utilize a common bus structure to reduce internal wiring.

1.3 Arithmetic Micro-operations

Arithmetic micro-operations execute fundamental numeric calculations on digital data stored in registers.

1.4 Logic Micro-operations

Logic micro-operations perform bitwise operations on non-numeric binary patterns stored in registers.

• AND (Masking): R1 ← R1 ∧ R2 (Used to clear selected bit positions to 0).
• OR (Selective Set): R1 ← R1 ∨ R2 (Used to set selected bit positions to 1).
• XOR (Selective Complement): R1 ← R1 ⊕ R2 (Used to invert selected bits or test equality).
• Complement (NOT): R1 ← R1 (Flips every bit in the register).

1.5 Shift Micro-operations

Shift micro-operations shift binary data laterally within registers to accomplish data alignment, bit manipulation, or multiplication/division by powers of two.

1.6 Arithmetic Logic Unit (ALU)

An Arithmetic Logic Unit (ALU) is a combined digital circuit that integrates arithmetic operations and logical operations into a unified functional block.

Core Concept: An ALU receives inputs from internal registers, processes data through multiplexed arithmetic and logic pathways according to selection control lines, and outputs results to a destination register.

2. Computer Organization and Design

2.1 Computer Instructions, Timing, Control, and Instruction Cycle

A computer instruction is a binary string specifying the exact micro-operations required to perform a task.

• Instruction Format: Composed of an Addressing Mode bit (I), Operation Code (Opcode), and Address field.
• Timing & Control Unit: Uses a master clock generator and a Sequence Counter (SC) decoded into sequential timing signals T₀, T₁, T₂, ..., T₁₅.

Standard Instruction Cycle Phases:

1. Fetch: Load instruction into IR and increment PC: IR ← M[AR], PC ← PC + 1
2. Decode: Decode opcode in IR, extract addressing mode I and target address into AR.
3. Read Effective Address: If indirect mode (I = 1), fetch memory operand address: AR ← M[AR].
4. Execute: Perform the sequence of micro-operations corresponding to the decoded instruction.

2.2 Memory Reference Instructions

Memory Reference Instructions directly interact with memory to read, store, or perform logical/arithmetic evaluations on stored words.

2.3 Input-Output and Interrupt Instructions

Input and Output (I/O) instructions manage communication between peripheral devices and the central processing system using flag registers FGI (Input Flag) and FGO (Output Flag).

• INP: AC(0-7) ← INPR, FGI ← 0 (Transfers character from Input Register to Accumulator).
• OUT: OUTR ← AC(0-7), FGO ← 0 (Transfers character from Accumulator to Output Register).
• SKI / SKO: Skip next instruction if input/output flag is set.
• ION / IOF: Set Interrupt Enable (IEN) flip-flop ON or OFF.

Interrupt Cycle: If an interrupt request occurs and IEN = 1, the processor saves the current return address into memory address 0 and branches to the interrupt service routine at address 1: M[0] ← PC, PC ← 1, IEN ← 0.

2.4 Design of a Basic Computer

The overall design of a basic computer combines execution hardware, registers, a common bus system, control hardware, and logic units into a functional system architecture.